Mobile radio communication systems are currently under development to provide global mobility with a wide range of services including telephony, paging, messaging, and broadband including Internet access. The Third Generation Partnership Project (3GPP) formed for technical development of the W-CDMA standard has five main UMTS standardization areas including the Radio Access Network, Core Network, Terminals, Services and System Aspects and GERAN.
A UMTS network consists of three interacting domains: (1) the Core Network (CN); (2) Universal Terrestrial Radio Access Network (UTRAN); and (3) User Equipment (UE). Wide band Code Division Multiple Access (W-CDMA) technology was selected for UTRA. UMTS W-CDMA is a Direct Sequence CDMA system where user data is multiplied by spreading codes for channelization, and scrambling codes for synchronization and scrambling.
UMTS has provisions for a fast power control mechanism employing closed loop power control. Open loop power control is also provided whereby the UE transmitter sets its output power to a specific value. Initial uplink and downlink transmission power levels are configured during set up of a dedicated channel via the open loop power control mechanism.
The UMTS fast power control mechanism employs two separate loops known as Transmit Power Control (TPC) loops: one for Uplink power and one for Downlink power, referred to as ULTPC and DLTPC, respectively. Both the ULTPC loop and DLTPC loop cycle at 1500 Hz meaning both loops are updated once per time slot. Alternately, both loops perform control processing during every timeslot. The update, however, may occur at a rate lower than once per time slot. The standard does not indicate a requirement for the processing delay, but only indicates the required performance (while hinting that a certain processing delay might be needed to achieve adequate performance).
The ULTPC loop gives the UE transmitter the ability to adjust its output power in accordance with one or more Transmit Power Control (TPC) commands received in the Downlink Dedicated Physical Channel (DL-DPCH) so as to keep the uplink signal level at a network designated level. The UE transmitter must be capable of changing the output power with a step size of 1, 2 and 3 dB, in the time slot immediately occurring after the TPC command is derived. The serving cell generates TPC commands and transmits the commands once per time slot. Upon reception of one or more TPC commands at the same time (i.e. from the cells in the active set), the UE derives a single TPC command for each time slot, combining multiple TPC commands if more than one is received at the same time.
Note that the target or desired SIR is an internal value in the UE which is derived from a target BLER value provided for every logical receive channel. The standard maintains that the target BLER be attained while the downlink power control loop is closed. Thus, the target SIR is a manifestation of the target BLER in the internal metrics of the UE.
The DLTPC loop functions to adjust the transmission quality, represented by the SIR, to a transmission quality target value. Based on data (e.g., pilot symbols) sent by the cell transmitter, the UE generates appropriate transmit power control (TPC) commands for transmission back to the network on the Uplink Dedicated Physical Control Channel (UL-DPCH). An ‘up’ power control command is sent back to the network when the estimated SIR is below the target value whereas a ‘down’ power control command is sent when the SIR is above the target specified by the Open Loop power control mechanism.
Thus, from the point of view of the UE transceiver, each TPC loop cycle requires a separate type of processing. In particular, for the DLTPC loop, downlink receive SIR estimation must be performed. For the ULTPC, TPC command decoding must be performed. From a scheduling perspective, however, both downlink and uplink transmit power control loops are constrained by the same limitation, namely the structure, format and timing separation of the DL-DPCH and UL-DPCCH time slot data fields. It is noted that SIR estimations do not necessarily need to be performed on the pilot fields. An advantage to performing it on the pilot field is coherent accumulation since the bits transmitted are known. Alternatively, however, the SIR estimation may be performed on the entire timeslot, though performance is lessened.
A timing diagram illustrating typical timing for prior art UE single receive path timing in CELL_DCH mode of reception is shown in FIG. 1. The receive downlink DPCH format, generally referenced 10, comprises within each time slot a first data field 12, TPC field 14, TFCI field 16, second data field 18 and a pilot field 20. The transmit uplink DPCCH format, generally referenced 22, comprises a pilot field 24, TFCI field 26 and TPC field 28 (and possibly additional fields).
In W-CDMA the downlink transmit stream is composed of radio frames, each 10 milliseconds long. Each frame is comprised of 15 timeslots of equal length. At a chip rate of 3.84 Mchips/s, each radio frame is 38400 chips long and each time slot is 2560 chips long. Each time slot is a time multiplexing of the DPDCH and DPCCH channels. The DPDCH is composed of two data field (i.e. Data1 and Data2) and the DPCCH is composed of a pilot field, a TPC field and a TFCI field. The lengths of the fields are as in accordance with the timeslot format designated at that point in time. Note that timeslot formats may change as fast as once every frame.
As indicated in FIG. 1, during each time slot, UE timing is constrained by several factors. The most severe timing constraint is the power control timing where two power control procedures, including one for the uplink power control loop and one for the downlink power control loop, are squeezed between the start point on the downlink receive stream and the end point on the uplink transmit stream. To complicate matters, these start and end points are dynamic and can change substantially over time where the range of interval lengths thus placing an even tighter constraint on real time performance.
Thus, there is a need for an efficient scheduling scheme that is capable of insuring the availability of data at the proper time and place such that the required time critical operations and tasks may be performed to meet the standard. Further, the system should provide the received data to the processor with minimal latency from the time of reception. It is also desirable for the scheduling scheme to be able to provide the received data to the processing point in a system comprising multiple receive data streams such as in W-CDMA transceivers whose typical reception scenarios include multipath propagation and the need to properly align multiple receive data streams.
In the case of multipath reception, the most delayed finger in the rake receiver architecture dictates the minimum timing difference between receive and transmit. As the time difference decreases, the time available for the required processing also decreases. The timing constraints worsen as the DL-UL timing offset becomes smaller and smaller. The nominal offset of 1024 chips but in accordance with the standard may get as low as a few hundred chips making the timing constraints even tighter.